Generally, as shown in FIG. 1 of the drawings, in an ATM network a plurality of digital data streams S1, . . . , Sn having different bit rates R1, . . . , Rn, respectively, (or at least one data stream having a certain bit rate) are input to a signal processing element SPE, and are output to a transmission path T operated at a further different bit rate RT.
For transmission via the transmission path T, the respective input data streams S1, . . . , Sn are “cut” or separated by the signal processing element SPE into a respective plurality of so-called ATM cells CSli, . . . , Csnk of a predetermined length including cell identifier codes as well as the respective information to be transmitted. The thus obtained ATM cells CSli, . . . , CSnk are temporarily stored or buffered in a buffer memory BUF_MEM and output to the single transmission path T operated at the specified bit rate RT. Within the output data stream, the respective ATM cells are alternately transmitted according to the amount of data to be transmitted in the corresponding data streams S1, . . . , Sn, while in case that no information is to be transmitted, a so-called empty-cell or blank cell (containing no information to be transmitted, but containing a specified sequence of bits representing that the cell is a blank cell) is inserted in the transmitted stream of ATM-cells.
The above mentioned cells transmitted via an ATM network have a standardized cell format as follows: each ATM cell consists of a header portion comprising five octets (or bytes, respectively) containing cell identifier codes, address codes etc., and a payload portion of forty-eight octets as the ATM service data units containing the information to be transmitted.
This principle of ATM transmission as briefly explained above is illustrated in FIG. 1. However, FIG. 1 illustrates the transmitter side only, and a corresponding (“reverted”) signal processing has to be conducted at the receiver side. That is, at the receiver side, the received data stream of ATM cells has to be buffered and the ATM cells are rejoined to thereby reconstruct the respective individual data streams on the basis of cell identifier codes of the respective ATM cells included in each header portion.
Such an arrangement at the sender side and the receiver side with a transmission path there between may already be assumed to constitute a (simple) ATM network operating according to the ATM standard. In particular, the bit rate at the sender input side and the bit rate at the receiver output side may be different from each other.
Recently, with the increasing progress in development of mobile communication, in addition to the mere “telephone” feature providing for transmission of audio data, i.e. pulse code modulated (PCM) speech data, an increased customer demand for various other services like information services has developed, which services are also commonly referred to as “value added services”. The information respectively provided by such services, however, has to be transmitted at different bit rates depending on the bandwidth required for the transmission of the respective information. Therefore, lately developments also implement the principle of ATM in connection with mobile communication according to the present status of GSM system, to which telecommunication system reference is made by way of example only.
FIG. 2 shows a simplified block diagram of an ATM link implemented in a GSM system with the indicated signal transmission direction being depicted for the downlink direction. That is, data output from a mobile switching center MSC via the corresponding MSC interface are transmitted via a PCM link (transmitting for example digital data like digital pulse code modulated speech data (voice data) and being illustrated as a bold arrow) to an associated buffer memory BUF_1. It is to be noted that this buffer memory also effects the conversion of the data received via the PCM link into ATM cells and vice versa (depending on the current signal transmission direction, i.e. uplink or downlink) and thus fulfills the function of the signal processing element SPE explained above with reference to FIG. 1. From the buffer memory BUF_1, the data are transmitted via an ATM link to a receiving side buffer memory BUF_2, which processes the received ATM cells such that the data can be transmitted via an output PCM link and a base transceiver station interface to a base transceiver station BTS. Due to the presence of the ATM link, as explained above, a need for two buffers (buffer memories) arises.
However, since the clock sources of the two PCM links associated to the mobile switching center MSC and the base transceiver station BTS, respectively, are not synchronized at all (the ATM link does not provide for any synchronization), there exists a difference in the clock frequencies of those PCM links. This clock difference (i.e. difference in sampling rate) will cause a buffer overflow or underflow because the data is not leaving the buffer at the same speed it arrives at the buffer.
For the sake of simplification of the further explanations, however, those two buffers connected to each other with an ATM link may be regarded as constituting a single signal processing element or buffer, respectively, which processing element connects two different PCM links PCM_IN and PCM_OUT. This model is shown in FIG. 3A of the drawings.
FIG. 3A depicts the situation of two separately, i.e. autonomously clocked PCM data streams clocked with sample rates CLK_1 and CLK_2, respectively, which are not synchronized at all, being connected to a single signal processing element or buffer, respectively. As briefly explained above, the PCM data streams (e.g. audio data streams) are independently clocked in such a way that the clock rates are not exactly the same. Consequently, after a certain time of operation, the buffer gets filled up when the output clock rate CLK_2 of the data stream PCM_OUT is lower than the input clock rate CLK_1 of the data stream PCM_IN. When the output clock rate CLK_2 of the data stream PCM_OUT is faster than the input clock rate CLK_1 of the data stream PCM_IN, the buffer runs out of data after a certain time, i.e. the buffer will become empty.
Stated in other words, as a result of the clock frequency difference between the clock rates CLK_1 and CLK_2, buffering problems such as overflow or underflow of the buffer will occur.
In case of overflow, new data arriving at the buffer will not be stored in the buffer and are therefore lost, resulting in a drawback that information is transmitted incomplete. In case of underflow, temporarily no data are available for transmission to the receiver side, so that the data transmission (or data output) as viewed from the receiver side will be temporarily interrupted.
In any case, even if the clock rates CLK_1, CLK_2 are almost the same and differ only slightly from one another, the above described problems still exist, although they will appear only very rarely.
Therefore, a conventionally known possibility to remove the problem was to add a sample rate converter SRC at the input side of the buffer which resamples the input PCM data (or audio data, respectively,) to thereby adapt the input sample raze (or clock rate) CLK_1 to the output sample rate CLK_2. FIG. 3B shows a schematic block diagram depicting such an earlier solution for a PCM—PCM sample rate adaptation.
However, this prior art solution has drawbacks such that an enormous amount of signal processing was required, which due to the data modification, to a certain extent, also influenced sound quality of a transmitted PCM audio stream. In general, it has to be expected that such a solution will adversely affect the quality of transmitted digital signals.